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INTEGRATED CIRCUITS
DATA SHEET
74HCT9046A PLL with bandgap controlled VCO
Product specification Supersedes data of March 1994 File under Integrated Circuits, IC06 1999 Jan 11
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
FEATURES * Low power consumption * Centre frequency up to 17 MHz (typ.) at VCC = 5.5 V * Choice of two phase comparators(1): - EXCLUSIVE-OR (PC1) - Edge-triggered JK flip-flop (PC2) * No dead zone of PC2 * Charge pump output on PC2, whose current is set by an external resistor Rb * Centre frequency tolerance 10% * Excellent voltage-controlled-oscillator (VCO) linearity * Low frequency drift with supply voltage and temperature variations * On chip bandgap reference * Glitch free operation of VCO, even at very low frequencies * Inhibit control for ON/OFF keying and for low standby power consumption * Operation power supply voltage range 4.5 to 5.5 V * Zero voltage offset due to op-amp buffering * Output capability: standard * ICC category: MSI. APPLICATIONS * FM modulation and demodulation where a small centre frequency tolerance is essential * Frequency synthesis and multiplication where a low jitter is required (e.g. Video picture-in-picture) * Frequency discrimination
(1) Rb connected between pin 15 and ground: PC2 mode, with PCPOUT at pin 2. Pin 15 left open or connected to VCC: PC1 mode with PC1OUT at pin 2.
74HCT9046A
GENERAL DESCRIPTION The 74HCT9046A is a high-speed Si-gate CMOS device. It is specified in compliance with "JEDEC standard no. 7A".
* Tone decoding * Data synchronization and conditioning * Voltage-to-frequency conversion * Motor-speed control. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 6 ns. SYMBOL fc PARAMETER VCO centre frequency
CONDITIONS C1 = 40 pF; R1 = 3 k; VCC = 5 V notes 1 and 2
TYP. 16
UNIT MHz
CI CPD
input capacitance power dissipation capacitance per package
3.5 20
pF pF
Notes 1. CPD is used to determine the dynamic power dissipation (PD in W) a) PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: b) fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo) = sum of the outputs. 2. Applies to the phase comparator section only (inhibit = HIGH). For power dissipation of the VCO and demodulator sections see Figs 26 to 28. ORDERING INFORMATION EXTENDED TYPE NUMBER 74HCT9046AN 74HCT9046AD PACKAGE PINS 16 16 PIN POSITION DIL16 SO16 MATERIAL plastic plastic CODE SOT38Z SOT109A
1999 Jan 11
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Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
PINNING SYMBOL GND PC1OUT/ PCPOUT COMPIN VCOOUT INH C1A C1B GND VCOIN DEMOUT R1 R2 PC2OUT SIGIN Rb VCC PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DESCRIPTION ground (0 V) (phase comparators) phase comparator 1 output/phase comparator pulse output comparator input VCO output inhibit input capacitor C1 connection A capacitor C1 connection B ground (0 V) (VCO) VCO input demodulator output resistor R1 connection resistor R2 connection phase comparator 2 output (current source adjustable with Rb) signal input bias resistor (Rb) connection supply voltage
GND PC1 OUT / PCPOUT COMP IN VCO OUT INH C1 A C1 B GND 1 2 3 4
74HCT9046A
16 V CC 15 14 13 Rb SIG IN PC2 OUT R2
9046A
5 6 7 8
MBD037 - 1
12
11 R1 10 9 DEM OUT VCO IN
Fig.1 Pin configuration.
LOGIC/FUNCTIONAL SYMBOLS AND DIAGRAMS
3 14 15
COMP IN SIG IN Rb
PC1OUT / PCPOUT PC2 OUT
2 3 14 6 7 11 12 15 9 5
COMP IN SIG IN C1 A C1 B R1 R2 Rb VCO IN INH
PLL 9046A
13
PC1OUT / PCPOUT PC2 OUT
2 13
6 7 11 12 9 5
C1 A C1 B R1 R2 VCO IN INH
MBD038 - 1
VCO OUT
4
VCO
DEM OUT
DEM OUT VCO OUT
10 4
10
MBD039 - 1
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1999 Jan 11
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Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
C1 C1A 6 C1B 7 VCO OUT COMP IN SIG IN 4 3 14
9046A
R2 12 R2 R1 11 R1 PHASE COMPARATOR 1 2 PC1OUT / PCPOUT R3
VCO
PHASE COMPARATOR 2
13 PC2 OUT 15 R b Rb R4 C2
5 INH
10
9
DEM OUT VCO IN Rs
MBD040 - 1
Fig.4 Functional diagram.
1999 Jan 11
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C1 6 C1A 7 C1B f OUT 4 VCOOUT COMP IN 3 f IN 14 SIG IN PC1 Vref2 12 R2 PCP R2 VCO R3 PC1 OUT / PCP OUT 2 V ref1 11 R1 R1 logic 1 D CP Q RD Q up
Philips Semiconductors
PLL with bandgap controlled VCO
5
logic 1 10 Rs DEM OUT V ref1 V ref2 D CP Q RD down Q CHARGE PUMP PC2 OUT 13 R4 C2 Rb 15 Rb V ref2 BAND GAP 9 VCO IN 5 INH
MBD102 - 1
74HCT9046A
Product specification
Fig.5 Logic diagram.
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
FUNCTIONAL DESCRIPTION The 74HCT9046A is a phase-locked-loop circuit that comprises a linear VCO and two different phase comparators (PC1 and PC2) with a common signal input amplifier and a common comparator input (see Fig.4). The signal input can be directly coupled to large voltage signals (CMOS level), or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the '9046A' forms a second-order loop PLL. The principle of this phase-locked-loop is based on the familiar HCT4046A. However extra features are built in, allowing very high performance phase-locked-loop applications. This is done, at the expense of PC3, which is skipped in this HCT9046A. The PC2 is equipped with a current source output stage here. Further a bandgap is applied for all internal references, allowing a small centre frequency tolerance. The details are summed up in the next section called: "Differences with respect to the familiar HCT4046A". If one is familiar with the HCT4046A already, it will do to read this section only. DIFFERENCES WITH RESPECT TO THE FAMILIAR HCT4046A * A centre frequency tolerance of maximum 10%. * The on board bandgap sets the internal references resulting in a minimal frequency shift at supply voltage variations and temperature variations. * The value of the frequency offset is determined by an internal reference voltage of 2.5 V instead of VCC - 0.7 V. In this way the offset frequency will not shift over the supply voltage range. * A current switch charge pump output on PC2 allows a virtually ideal performance of PC2. The gain of PC2 is independent of the voltage across the low-pass filter. Further a passive low-pass filter in the loop achieves an active performance now. The influence of the parasitic capacitance of the PC2 output plays no role here, resulting in a true correspondence of the output correction pulse and the phase difference even up to phase differences as small as a few nanoseconds. * Because of its linear performance without dead zone, higher impedance values for the filter, hence lower C-values, can now be chosen. Correct operation will not be influenced by parasitic capacitances as in the instance with voltage source output of the 4046A. * No PC3 on pin 15 but instead a resistor connected to GND, which sets the load/unload currents of the charge pump (PC2). * Extra GND pin at pin 1 to allow an excellent FM demodulator performance even at 10 MHz and higher. * Combined function of pin 2. If pin 15 is connected to VCC (no bias resistor Rb) pin 2 has its familiar function viz. output of PC1. If at pin 15 a resistor (Rb) is connected to GND it is assumed that PC2 has been chosen as phase comparator. Connection of Rb is sensed by internal circuitry and this changes the function of pin 2 into a lock detect output (PCPOUT) with the same characteristics as PCPOUT of pin 1 of the well known 74HCT4046A.
74HCT9046A
* The inhibit function differs. For the HCT4046A a HIGH level at the inhibit input (INH) disables the VCO and demodulator, while a LOW level turns both on. For the 74HCT9046A a HIGH level on the inhibit input disables the whole circuit to minimize standby power consumption. VCO The VCO requires one external capacitor C1 (between C1A and C1B) and one external resistor R1 (between R1 and GND) or two external resistors R1 and R2 (between R1 and GND, and R2 and GND). Resistor R1 and capacitor C1 determine the frequency range of the VCO. Resistor R2 enables the VCO to have a frequency offset if required (see Fig.5). The high input impedance of the VCO simplifies the design of the low-pass filters by giving the designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass filter, a demodulator output of the VCO input voltage is provided at pin 10 (DEMOUT). The DEMOUT voltage equals that of the VCO input. If DEMOUT is used, a load resistor (Rs) should be connected from pin 10 to GND; if unused, DEMOUT should be left open. The VCO output (VCOOUT) can be connected directly to the comparator input (COMPIN), or connected via a frequency-divider. The VCO output signal has a duty factor of 50% (maximum expected deviation 1%), if the VCO input is held at a constant DC level. A LOW level at the inhibit input (INH) enables the VCO and demodulator, while a HIGH level turns both off to minimize standby power consumption.
1999 Jan 11
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Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
Phase comparators The signal input (SIGIN) can be directly coupled to the self-biasing amplifier at pin 14, provided that the signal swing is between the standard HC family input logic levels. Capacitive coupling is required for signals with smaller swings. PHASE COMPARATOR 1 (PC1) This circuit is an EXCLUSIVE-OR network. The signal and comparator input frequencies (fi) must have a 50% duty factor to obtain the maximum locking range. The transfer characteristic of PC1, assuming ripple (fr = 2fi) is suppressed, is: V CC V DEMOUT = ---------- ( SIGIN - COMPIN ) where: VDEMOUT is the demodulator output at pin 10. VDEMOUT = VPC1OUT (via low-pass). The phase comparator gain is: V CC K p = ---------- ( V r ) The average output voltage from PC1, fed to the VCO input via the low-pass filter and seen at the demodulator output at pin 10 (VDEMOUT), is the resultant of the phase differences of signals (SIGIN) and the comparator input (COMPIN) as shown in Fig.6. The average of VDEMOUT is equal to 12VCC when there is no signal or noise at SIGIN and with this input the VCO oscillates at the centre frequency (fc). Typical waveforms for the PC1 loop locked at fc are shown in Fig.7. This figure also shows the actual waveforms across the VCO capacitor at pins 6 and 7 (VC1A and VC1B) to show the relation between these ramps and the VCOOUT voltage. The frequency capture range (2fc) is defined as the frequency range of input signals on which the PLL will lock if it was initially out-of-lock. The frequency lock range (2fL) is defined as the frequency range of the input signals on which the loop will stay locked if it was initially in lock. The capture range is smaller or equal to the lock range. With PC1, the capture range depends on the low-pass filter characteristics and can be made as large as the lock range. This configuration remains locked even with very noisy input signals. Typical behaviour of this type of phase comparator is that it may lock to input frequencies close to the harmonics of the VCO centre frequency. PHASE COMPARATOR 2 (PC2) This is a positive edge-triggered phase and frequency detector. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not important. PC2 comprises two D-type flip-flops, control gating and a 3-state output stage with sink and source transistors acting as current sources, henceforth called charge pump output of PC2. The circuit functions as an up-down counter (Fig.5) where SIGIN causes an up-count and COMPIN a down count. The current switch charge pump output allows a virtually ideal performance of PC2, due to appliance of some pulse overlap of the up and down signals. See Fig.8a.
74HCT9046A
1999 Jan 11
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Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
V CC V DEMOUT(AV)
MBD101 - 1
1/2V CC
0
0o
90 o
PCIN
180 o
V CC V DEMOUT = V PC1OUT = ---------- ( SIGIN - COMPIN ) PCIN = ( SIGIN - COMPIN )
Fig.6 Phase comparator 1; average output voltage as a function of input phase difference.
SIGN IN
COMP IN VCO OUT
PC1 OUT VCC GND
VCO IN
VC1A
pin 6
VC1B
pin 7
MBD100
Fig.7 Typical waveforms for PLL using phase comparator 1; loop-locked at fc. 1999 Jan 11 8
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
The pump current IP is independent from the supply voltage and is set by the internal bandgap reference of 2.5 V. 2.5 I P = 17 x ------- ( A ) Rb Rb is the external bias resistor between pin 15 and ground. The current and voltage transfer function of PC2 are shown in Fig.9. The phase comparator gain is: IP K p = ------- ( A r ) 2 Typical waveforms for the PC2 loop locked at fc are shown in Fig.10. When the frequencies of SIGIN and COMPIN are equal but the phase of SIGIN leads that of COMPIN, the up output driver at PC2OUT is held `ON' for a time corresponding to the phase difference (PCIN). When the phase of SIGIN lags that of COMPIN, the down or sink driver is held `ON'. When the frequency of SIGIN is higher than that of COMPIN, the source output driver is held `ON' for most of the input signal cycle time and for the remainder of the cycle time both drivers are `OFF' (3-state). If the SIGIN frequency is lower than the COMPIN frequency, then it is the sink driver that is held `ON' for most of the cycle. Subsequently the voltage at the capacitor (C2) of the low-pass filter connected to PC2OUT varies until the signal and comparator inputs are equal in both phase and frequency. At this stable point the voltage on C2 remains constant as the PC2 output is in 3-state and the VCO input at pin 9 is a high impedance. Also in this condition the signal at the phase comparator pulse output (PCPOUT) has a minimum output pulse width equal to the overlap time, so can be used for indicating a locked condition. Thus for PC2 no phase difference exists between SIGIN and COMPIN over the full frequency range of the VCO. Moreover, the power dissipation due to the low-pass filter is reduced because both output drivers are OFF for most of the signal input cycle. It should be noted that the PLL lock range for this type of phase comparator is equal to the capture range and is independent of the low-pass filter. With no signal present at SIGIN the VCO adjust, via PC2, to its lowest frequency. By using current sources as charge pump output on PC2, the dead zone or backlash time could be reduced to zero. Also, the pulse widening due to the parasitic output capacitance plays no role here. This enables a linear transfer function, even in the vicinity of the zero crossing. The differences between a voltage switch charge pump and a current switch charge pump are shown in Fig.11. The design of the low-pass filter is somewhat different when using current sources. The external resistor R3 is no longer present when using PC2 as phase comparator. The current source is set by Rb. A simple capacitor behaves as an ideal integrator now, because the capacitor is charged by a constant current. The transfer function of the voltage switch charge pump may be used. In fact it is even more valid, because the transfer function is no longer restricted for small changes only. Further the current is independent from both the supply voltage and the voltage across the filter. For one that is familiar with the low-pass filter design of the 4046A a relation may show how Rb relates with a fictive series resistance, called R3'. This relation can be derived by assuming first that a voltage controlled switch PC2 of the 4046A is
74HCT9046A
connected to the filter capacitance C2 via this fictive R3' (see Fig.8b). Then during the PC2 output pulse the charge current equals: V CC - V C2 ( 0 ) I P = ---------------------------------R3' With the initial voltage VC2(0) at:
1 2VCC
2.5 = 2.5 V, I P = -------R3'
As shown before the charge current of the current switch of the 9046A is: 2.5 I P = 17 x ------Rb Hence: Rb R3' = ------ ( ) 17 Using this equivalent resistance R3' for the filter design the voltage can now be expressed as a transfer function of PC2; assuming ripple (fr = fi) is suppressed, as: 5 K PC2 = ------ ( V r ) 4 Again this illustrates the supply voltage independent behaviour of PC2. Examples of PC2 combined with a passive filter are shown in Figs 12 and 13. Figure 12 shows that PC2 with only a C2 filter behaves as a high-gain filter. For stability the damped version of Fig.13 with series resistance R4 is preferred. Practical design values for Rb are between 25 and 250 k with R3' = 1.5 to 15 k for the filter design. Higher values for R3' require lower values for the filter capacitance which is very advantageous at low values the loop natural frequency n.
1999 Jan 11
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Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
VCC up
VCC
IP PC2 OUT
up
IP down C2
R3' IP down
PC2 OUT VC2 OUT C2
MBD099
= PCIN
pulse overlap of approximately 15 ns
MBD046 - 1
a.
b.
a. At every , even at zero both switches are closed simultaneously for a short period (typically 15 ns). b. Comparable voltage-controlled switch.
Fig.8 The current switch charge pump output of PC2.
V CC IP V DEMOUT(AV)
MSB306 - 1
IP x R PCIN = SIGIN COMPIN 0 1/2V CC
IP 0 2 0 PCIN 2 2 0 PCIN 2
a.
Two kinds of transfer functions may be regarded: IP a. The current transfer: pump current ------- PCIN 2
b.
b. The voltage transfer; this transfer can be observed at PC2OUT by connecting a resistor (R = 10 k) between PC2OUT and 12VCC; 5 V DEMOUT = V PC2OUT = ------ PCIN 4
Fig.9 Phase comparator 2.
1999 Jan 11
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Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
SIG IN
COMP IN VCO OUT
UP OPC IN DOWN
CURRENT AT PC2 OUT high impedance OFF state, (zero current) PC2 OUT /VCO IN
PCPOUT The pulse overlap of the up and down signals (typically 15 ns).
MBD047 - 1
Fig.10 Timing diagram for PC2.
2.75
2.75
VCO IN
VCO IN
(1)
2.50
(1)
2.50
(2)
2.25 25 0 phase error (ns) 25
2.25 25 0 phase error (ns) 25
a.
a. Response with traditional voltage-switch charge-pump PC2OUT (4046A). (1) Due to parasitic capacitance on PC2OUT. (2) Backlash time (dead zone). b. Response with current switch charge-pump PC2OUT as applied in the HCT9046A.
b.
MBD043
Fig.11 The response of a locked-loop in the vicinity of the zero crossing of the phase error.
1999 Jan 11
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Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
LOOP FILTER COMPONENT SELECTION
74HCT9046A
A
IP IP 17 C2 Rb INPUT OUTPUT 1/A 1 F ( j )
1/ A
1
MBD045 - 1
a.
Rb a. 1 = ------ x C2 = R3' x C2 17 1 1 b. Amplitude characteristic: F ( j ) = ---------------------------- ---------1 A + j 1 j 1 c. Pole zero diagram.
b.
c.
Fig.12 Simple loop filter for PC2 without damping.
A
IP IP 17 R4 Rb INPUT C2 OUTPUT m O 1/ 2 1/ A 1 F ( j )
1/ A
1
1 /
2
MBD044 - 1
a.
Rb a. 1 = ------ x C2 = R3' x C2 17 2 = R4 x C2 1 + j 2 b. Amplitude characteristic: F ( j ) = ---------------------------1 A + j 1 c. Pole zero diagram. A = DC gain limit, due to leakage.
b.
c.
Fig.13 Simple loop filter for PC2 with damping.
1999 Jan 11
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Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
RECOMMENDED OPERATING CONDITIONS FOR 74HCT SYMBOL VCC VI VO Tamb tr, tf PARAMETER DC supply voltage DC input voltage DC output voltage operating ambient temperature input rise and fall times (pin 5) see DC and AC Characteristics VCC = 4.5 V CONDITIONS MIN. 4.5 0 0 -40 -40 -
74HCT9046A
TYP. 5.0 - - - - 6
MAX. 5.5 VCC VCC +85 +125 500
UNIT V V V C C ns
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK IOK IO ICC; IGND Tstg Ptot PARAMETER DC supply voltage DC input diode current DC output diode current DC output source or sink current DC VCC or GND current storage temperature total power dissipation per package note 1 plastic DIL plastic mini-pack (SO) Note 1. Temperature range: -40 to +125 C. above +70 C: derate linearly with 12 mW/K above +70 C: derate linearly with 8 mW/K - - 750 500 mW mW for VI < -0.5 V or VI > VCC + 0.5 V for VO < -0.5 V or VO > VCC + 0.5 V for -0.5 V < VO < VCC + 0.5 V CONDITIONS - - - - -65 MIN. -0.5 MAX. +7 20 20 25 50 +150 V mA mA mA mA C UNIT
1999 Jan 11
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Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
DC CHARACTERISTICS FOR 74HCT Voltages are referenced to GND (ground = 0 V). Tamb (C) SYMBOL PARAMETER MIN. Phase comparator section VIH DC coupled HIGH level input voltage SIGIN, COMPIN 3.15 2.4 - 3.15 - 3.15 - V 4.5 +25 -40 to +85 -40 to +125 UNIT
74HCT9046A
TEST CONDITIONS VCC (V) VI (V) OTHER
TYP. MAX. MIN. MAX. MIN. MAX.
-
VIL
DC coupled LOW - level input voltage SIGIN, COMPIN HIGH level 4.4 output voltage PCPOUT, PCnOUT 3.98
2.1
1.35
-
1.35
-
1.35
V
4.5
-
VOH
4.5
-
4.4
-
4.4
-
V
4.5
VIH or VIL VIH or VIL VIH or VIL VIH or VIL VCC or GND VIH or VIL
IO = -20 A
4.32
-
3.84
-
3.7
-
V
4.5
IO = -4.0 mA
VOL
LOW level - output voltage PCPOUT, PCnOUT -
0
0.1
-
0.1
-
0.1
V
4.5
IO = -20 A
0.15
0.26
-
0.33
-
0.4
V
4.5
IO = -4.0 mA
II
input leakage current SIGIN, COMPIN 3-state OFF-state current PC2OUT input resistance SIGIN, COMPIN
-
-
30
-
38
-
45
A
5.5
IOZ
-
-
0.5
-
5.0
-
10.0 A
5.5
VO = VCC or GND
RI
-
250
-
-
-
-
-
k
4.5
VI at self-bias operating point; VI = 0.5 V; see Figs 14 to 16 - - Rb = 40 k
Rb IP
bias resistance charge pump current
25
-
250
-
- -
- -
- -
k mA
4.5 4.5
0.53 1.06 2.12 -
1999 Jan 11
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Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Tamb (C) SYMBOL PARAMETER MIN. VCO section VIH DC coupled HIGH level input voltage INH 2.0 1.6 - 2.0 - 2.0 - V +25 -40 to +85 -40 to +125 UNIT
TEST CONDITIONS VCC (V) VI (V) OTHER
TYP. MAX. MIN. MAX. MIN. MAX.
4.5 - to 5.5 4.5 - to 5.5 4.5 VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIH or VIL VCC or GND - - - - - - over the range specified for R1 IO = -20 A
VIL
DC coupled LOW - level input voltage INH HIGH level output voltage VCOOUT 4.4
1.2
0.8
-
0.8
-
0.8
V
VOH
4.5
-
4.4
-
4.4
-
V
3.98
4.32
-
3.84
-
3.7
-
V
4.5
IO = -4.0 mA
VOL
LOW level output voltage VCOOUT
-
0
0.1
-
0.1
-
0.1
V
4.5
IO = 20 A
-
0.15
0.26
-
0.33
-
0.4
V
4.5
IO = 4.0 mA
VOL
LOW level output voltage C1A, C1B input leakage current INH and VCOIN resistance resistance capacitance operating voltage range at VCOIN
-
-
0.40
-
0.47
-
0.54
V
4.5
IO = 4.0 mA
II
-
-
0.1
-
1.0
-
1.0
A
5.5
R1 R2 C1 VVCOIN
3 3 40 1.1 1.1 1.1
- - - - - -
300 300 no limit 3.4 3.9 4.4
- - - - - -
- - - - - -
- - - - - -
- - - - - -
k k pF V V V
4.5 4.5 4.5 4.5 5.0 5.5
1999 Jan 11
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Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Tamb (C) SYMBOL PARAMETER MIN. Demodulator section Rs resistance 50 - 300 - - - - k 4.5 +25 -40 to +85 -40 to +125 UNIT
TEST CONDITIONS VCC (V) VI (V) OTHER
TYP. MAX. MIN. MAX. MIN. MAX.
-
at Rs > 300 k the leakage current can influence VDEMOUT VI = VVCOIN = 12VCC; values taken over Rs range, see Fig.17 VDEMOUT = 1 V 2 CC
VOFF
offset voltage VCOIN to VDEMOUT
-
20
-
-
-
-
-
mV
4.5
-
RD
dynamic output resistance at DEMOUT quiescent supply current (disabled) additional quiescent supply current per input pin for unit load coefficient is 1; note 1; VI = VCC - 2.1 V
-
25
-
-
-
-
-
4.5
-
Quiescent supply current ICC - - 8.0 - 80.0 - 160.0 A 5.5 - pin 5 at VCC
ICC
-
100
360
-
450
-
490
A
4.5
-
other inputs at VCC or GND
Note 1. The value of additional quiescent supply current (ICC) for a unit load of 1 is given above. To determine ICC per input, multiply this value by the unit load coefficient shown in Table 1. Table 1 Unit load coefficient table. INPUT INH UNIT LOAD COEFFICIENT 1.00
1999 Jan 11
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Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
MBD108
800 RI (k )
MGA956 - 1
II VI
600
400 VCC = 4.5 V
200
self-bias operating point
5.5 V
VI
0 1/2VCC 0.25
1/2V CC
VI (V)
1/2VCC 0.25
Fig.14 Typical input resistance curve at SIGIN, COMPIN.
Fig.15 Input resistance at SIGIN; COMPIN with VI = 0.5 V at self-bias point.
MGA957
5 VCC = 5.5 V II ( A) 4.5 V
60 V OFF (mV) 40
MGA958
20 0 0 4.5 V 5.5 V 20 5.5 V VCC = 4.5 V
5 1/2 VCC 0.25
40 1/2 VCC V I (V) 1/2 VCC 0.25 1/2 VCC 2 1/2 V CC 1/2 VCC 2 V VCOIN (V)
___ Rs = 50 k. - - - Rs = 300 k.
Fig.16 Input current at SIGIN; COMPIN with VI = 0.5 V at self-bias point. 1999 Jan 11 17
Fig.17 Offset voltage at demodulator output as a function of VCOIN and Rs.
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb (C) SYMBOL PARAMETER MIN. Phase comparator section tPHL/tPLH propagation delay SIGIN, COMPIN to PC1OUT propagation delay SIGIN, COMPIN to PCPOUT 3-state output enable time SIGIN, COMPIN to PC2OUT 3-state output enable time SIGIN, COMPIN to PC2OUT output transition time - 23 40 - 50 - 60 ns +25 TYP. MAX. -40 to +85 MIN. MAX. -40 to +125 MIN. MAX. UNIT
74HCT9046A
TEST CONDITION VCC (V) WAVEFORMS
4.5
Fig.18
tPHL/tPLH
-
35
68
-
85
-
102
ns
4.5
Fig.18
tPZH/tPZL
-
30
56
-
70
-
84
ns
4.5
Fig.19
tPHZ/tPLZ
-
36
65
-
81
-
98
ns
4.5
Fig.19
tTHL/tTLH Vi(p-p)
-
7 15
15 -
- -
19 -
- -
22 -
ns mV
4.5 4.5
Fig.18 fi = 1 MHz
AC coupled input - sensitivity (peak-to-peak value) at SIGNIN or COMPIN
1999 Jan 11
18
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Tamb (C) SYMBOL PARAMETER MIN. VCO section f/T frequency stability with temperature change - - - 0.06 - - - %/K +25 TYP. MAX. -40 to +85 MIN. MAX. -40 to +125 MIN. MAX. UNIT
TEST CONDITION VCC (V) WAVEFORMS
4.5
VVCOIN = 12VCC; recommended range: R1 = 10 k; R2 = 10 k; C1 = 1 nF; Figs 20 to 22 VVCOIN = 3.9 V; R1 = 10 k; R2 = 10 k; C1 = 1 nF VVCOIN = 12VCC; R1 = 4.3 k; R2 = ; C1 = 40 pF; Figs 23 and 31 R1 = 100 k; R2 = ; C1 = 100 pF; Figs 24 and 25
fc
centre frequency tolerance
-10
-
+10
-
-
-
-
%
5.0
fc
VCO centre 11.0 frequency (duty factor = 50%)
15.0
-
-
-
-
-
MHz
4.5
fVCO
VCO frequency linearity
-
0.4
-
-
-
-
-
%
4.5
VCO
duty factor at VCOOUT
-
50
-
-
-
-
-
%
4.5
1999 Jan 11
19
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
SIG IN , COMP IN INPUTS
V M (1)
t PHL PCPOUT , PC1OUT , OUTPUTS
MBD106
t PLH
V M (1)
t THL
t TLH
(1) VM = 12VCC; VI = GND to VCC.
Fig.18 Waveforms showing input (SIGIN and COMPIN) to output (PCPOUT and PC1OUT) propagation delays and the output transition times.
SIG IN INPUT
VM(1)
COMP IN INPUT t PZH PC2 OUT OUTPUT
VM(1) t PHZ 90% VM
(1)
t PZL
t PLZ
10%
MGA941
(1) VM = 12VCC; VI = GND to VCC.
Fig.19 Waveforms showing the 3-state enable and disable times for PC2OUT. 1999 Jan 11 20
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
20 f (%) 10
MBD115
f (%)
15
MBD116
10
5
0
0
V CC = 10 5.5 V 4.5 V 20 50 0 50 100 150 o T amb ( C)
5
V CC = 5.5 V 4.5 V
10
15
50
0
50
a.
a. R1 = 3 k; R2 = ; C1 = 100 pF. b. R1 = 10 k; R2 = ; C1 = 100 pF.
b.
100 150 Tamb ( oC)
Fig.20 Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter.
10 f (%) 5
MBD124
V CC =
5.5 V 4.5 V
f (%)
15 10 5 0
MBD117
V CC = 5.5 V
0
5 10 15
5
4.5 V 50 0 50 100 150 Tamb ( oC)
10
50
0
50
a.
100 150 o T amb ( C)
20
b.
a. R1 = 300 k; R2 = ; C1 = 100 pF. b. R1 = ; R2 = 3 k; C1 = 100 pF.
Fig.21 Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter.
1999 Jan 11
21
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
8
MBD118
10
MBD119
f (%)
4
f (%)
5 0 0 4 V CC = 5.5 V 8 4.5 V 5 5.5 V V CC = 4.5 V
12
50
0
50
a.
a. R1 = ; R2 = 10 k; C1 = 100 pF. b. R1 = ; R2 = 300 k; C1 = 100 pF.
100 150 Tamb ( oC)
10
50
0
50
b.
100 150 Tamb ( oC)
Fig.22 Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter.
1999 Jan 11
22
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
30 f VCO (MHz) 20 V CC = 4.5 V 10 5.5 V
MBD112
30 f VCO (kHz) 20
MBD113
V CC = 4.5 V 5.5 V
10
0 0 2 4 6 V VCOIN (V)
0 0 2 4 V VCOIN (V) 6
a.
b.
handbook, halfpage
800
MBD120 - 1
handbook, halfpage
400
MBD111 - 1
f VCO (kHz) 600
V CC = 5.5 V 4.5 V
f VCO (Hz) 300
V CC = 5.5 V frequency 4.5 V frequency
400
200
200
100
0 0 2 4 V VCOIN (V) 6
0 0 2 4 V VCOIN (V) 6
c.
a. R1 = 4.3 k; C1 = 39 pF. b. R1 = 4.3 k; C1 = 100 nF. c. R1 = 300 k; C1 = 39 pF. d. R1 = 300 k; C1 = 100 nF.
d.
Fig.23 Graphs showing VCO frequency as a function of the VCO input voltage (VVCOIN).
1999 Jan 11
23
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
MGA937 - 1
4 f VCO (%) C1 = 1 F 4.5 V 5.5 V
MBD114
f f2 fc f'c f1
0
C1 = 39 pF 4.5 V
4 V min 1/2V CC V max V VCOIN 8 1 f1 + f2 f c = -------------2 f c - f c linearity = --------------- x 100% fc 10 10 2
3 R1 (k) 10
5.5 V
R2 = and V = 0.5 V.
Fig.24 Definition of VCO frequency linearity: V = 0.5 V over the VCC range.
Fig.25 Frequency linearity as a function of R1, C1 and VCC.
1
MBD121
1 VCC = 5.5 V C1 = 39 pF 4.5 V C1 = 39 pF
MBD110
PD (W)
VCC = 5.5 V C1 = 1 F 4.5 V C1 = 1 F
PD (W)
10 1
10
5.5 V C1 = 39 pF 4.5 V C1 = 39 pF
1
5.5 V 4.5 V C1 = 1 F
10 2
0
100
200
R1 (k)
300
10 2
0
100
200
R2 (k)
300
R2 = .
R1 = .
Fig.26 Power dissipation as a function of component values.
Fig.27 Power dissipation as a function of component values.
1999 Jan 11
24
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
APPLICATION INFORMATION
10 3
MBD109
74HCT9046A
This information is a guide for the approximation of values of external components to be used with the 74HCT9046A in a phase-locked-loop system. Values of the selected components should be within the rages shown in Table 2.
P DEM (W) V CC = 10 4 4.5 V 5.5 V
Table 2 Survey of components. COMPONENT R1 R2 R1 + R2 C1 VALUE between 3 k and 300 k between 3 k and 300 k parallel value >2.7 k >40 pF
10 5 10
102
R s (k)
10 3
Fig.28 Typical power dissipation.
Table 3 Design considerations for VCO section. SUBJECT VCO frequency without extra offset PHASE COMPARATOR DESIGN CONSIDERATION VCO frequency characteristic With R2 = and R1 within the range 3 k < R1 < 300 k, the characteristics of the VCO operation will be as shown in Fig.29a. (Due to R1, C1 time constant a small offset remains when R2 = ). Selection of R1 and C1 Given fc, determine the values of R1 and C1 using Fig.31. Given fmax and fc determine the values of R1 and C1 using Fig.31; use Fig.33 to obtain 2fL and then use this to calculate fmin. VCO frequency characteristic With R1 and R2 within the ranges 3 k < R1 < 300 k < R2 < 300 k, the characteristics of the VCO operation is as shown in Fig.29b. Selection of R1, R2 and C1 Given fc and fL determine the value of product R1C1 by using Fig.33. Calculate foff from the equation foff = fc - 1.6fL. Obtain the values of C1 and R2 by using Fig.32. Calculate the value of R1 from the value of C1 and the product R1C1. VCO adjusts to fc with PCIN = 90 and VVCOIN = 12VCC. VCO adjusts to foffset with PCIN = -360 and VVCOIN = minimum.
PC1, PC2
PC1 PC2 VCO frequency with extra offset
PC1, PC2
PC1, PC2
PLL conditions with no PC1 signal at the SIGIN input PC2
1999 Jan 11
25
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
MGA938 - 1
f VCO
f max fc f min 1.1 V 1/2VCC VCC 1.1 V VCC VCO IN 2f L due to R1,C1
a.
MGA939 - 1
f VCO f max fc f min f off 0.6f L due to R2,C1 2f L due to R1,C1
1.1 V
1/2VCC
VCC
1.1 V
b.
VCC VCO IN
a. Operating without offset; fc = centre frequency; 2fL = frequency lock range. b. Operating with offset; fc = centre frequency; 2fL = frequency lock range.
Fig.29 Frequency characteristic of VCO.
1999 Jan 11
26
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
Filter design considerations for PC1 and PC2 of the HCT9046A
74HCT9046A
Figure 30 shows some examples of passive and active filters to be used with the phase comparators of the HCT9046A. Transfer functions of phase comparators and filters are given in Table 4. Table 4 Transfer functions of phase comparators and filters. PHASE COMPARATOR PC1 Fig.30 a. FILTER TYPE passive filter without damping passive filter with damping active filter with damping passive filter with damping TRANSFER FUNCTION 1 F ( j ) = -------------------1 + j 1 1 + j 2 F ( j ) = --------------------------------------1 + j ( 1 + 2 ) 1 + j 2 1 + j 2 F ( j ) = ---------------------------- -------------------j 1 1 A + j 1 1 + j 2 1 + j 2 F ( j ) = ---------------------------- -------------------j 1 1 A + j 1 A = 105 = limit DC gain e. active filter with damping 1 + j 2 1 + j 2 F ( j ) = ---------------------------- -------------------j 1 1 A + j 1 A = 105 = DC gain amplitude EXPLANATION V CC K PC1 = ---------- V r 1 = R3 x C2; 2 = R4 x C2; 3 = R4 x C3; A = 105 = DC gain amplitude
b.
c.
PC2
d.
5 K PC2 = ------ V r 4 1 = R3' x C2; 2 = R4 x C2; 3 = R4 x C3; R3' = Rb/17; Rb = 25 to 250 k
1999 Jan 11
27
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
PC1
CIRCUIT
F(j) R3 C2
AMPLITUDE CHARACTERISTIC
POLE ZERO DIAGRAM
1/ 1
X 1/
1
a.
F(j) R3 C3 R4 1/ 1 2 C2 1/ 2 1/ 3 O 1/ 2 X 1
1 2
b.
A C3 C2 R4 R3 A 1/ A 1 1/ 2 1/ 3 O 1/ 2 X 1/ A 1
c.
PC2
A R3' R4 AR3' C2 1/A 1 1/ 2 1/ 3 O 1/ 2 X 1/ A 1
d.
A C3 C2 R4 R3' A 1/ 2 1/ 3 O 1/ 2 X 1/ A 1
1/A 1
MBD107 - 1
e. Fig.30 Passive and active filters for HCT9046A.
1999 Jan 11
28
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
General design consideration. SUBJECT PLL locks on harmonics at centre frequency Noise rejection at signal input AC ripple content when PLL is locked PHASE COMPARATOR PC1 PC2 PC1 PC2 PC1 PC2 yes no high low fr = 2fi; large ripple content at PCIN = 90 fr = fi; small ripple content at PCIN = 0
74HCT9046A
DESIGN CONSIDERATION
1999 Jan 11
29
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
10 8 fc (Hz)
MBD103 - 1
R1 = 3 k R1 = 10 k
10 7
10 6
R1 = 150 k R1 = 300 k
10 5
10 4
VCC = 10 3 5.5 V 4.5 V
5.5 V 4.5 V
10 2 5.5 V 4.5 V 5.5 V 4.5 V 10 1 10 10 2 10 3 10 4 10 5 10 6 C1 (pF) 107
R2 = ; VVCOIN = 12VCC; INH = GND; Tamb = 25 C.
Fig.31 Typical value of VCO centre frequency (fc) as a function of C1.
1999 Jan 11
30
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
10 8 foff (Hz) R2 = 3 k 10
7
MBD104
R2 = 10 k
10 6
R2 = 150 k R2 = 300 k
10 5
10 4
VCC = 4.5 V - 5.5 V 10 3 4.5 V - 5.5 V
10 2 4.5 V - 5.5 V 4.5 V - 5.5 V 10 1 10 10 2 10 3 10 4 10 5 10 6 107
C1 (pF)
R1 = ; VVCOIN = 12VCC; INH = GND; Tamb = 25 C.
Fig.32 Typical value of frequency offset as a function of C1.
1999 Jan 11
31
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
10 8 2f L (Hz)
MBD105 - 1
10 7
10 6
10 5
10 4
10 3
10 2
VCC = 5.5 V 4.5 V 10 10 7 10 6 10 5 10 4 10 3 10 2 10 1 R1C1 (s) 1
2f L K v = ------------------------------------ 2 ( r s V ) V VCOIN range VVCOIN = 1.1 to (VCC - 1.1) V.
Fig.33 Typical frequency lock range 2fL as a function of the product R1 and C1.
1999 Jan 11
32
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
PLL design example The frequency synthesizer used in the design example shown in Fig.34 has the following parameters: Output frequency: 2 MHz to 3 MHz. Frequency steps: 100 kHz. Settling time: 1 ms. Overshoot: <20%. The open loop gain is: H (s) x G (s) = Kp x Kf x Ko x Kn and the closed loop: x K Kp x Kf x Ko u n ------ = ----------------------------------------------------1 + Kp x Kf x Ko x Kn i where: Kp = phase comparator gain Kf = low-pass filter transfer gain Ko = Kv/s VCO gain Kn = 1n divider ratio. The programmable counter ratio Kn can be found as follows: f OUT 2 MHz N min = ----------- = --------------------- = 20 f step 100 kHz N max f OUT 3 MHz = ----------- = --------------------- = 30 f step 100 kHz The gain of the phase comparator PC2 is: 5 K p = ------------ = 0.4V r 4x Using PC2 with the passive filter as shown in Fig.34 results in a high gain loop with the same performance as a loop with an active filter. Hence loop filter equations as for a high gain loop should be used. The current source output of PC2 can be simulated then with a fictive filter resistance: Rb R3' = -----17 The transfer functions of the filter is given by: 1 + s 2 K f = ----------------s 2 Where: 1 = R3' x C2. 2 = R4 x C2. The characteristic equation is: 1 + Kp x Kf x Ko x Kn This results in: 1 + s 2 K v 1 + K p ----------------- ----- K n = 0 - s 1 s or: 2 2 s + sK p K v K n ---- + K p K v K n 1 = 0 1 This can be written as: s + 2 n s + ( n )
2 2
74HCT9046A
seen that the damping ratio = 0.707 will produce an overshoot of less than 20% and settle to within 5% at nt = 5. The required settling time is 1 ms. This results in: 3 5 5 n = -- = -------------- = 5 x 10 r s t 0.001 Rewriting the equation for natural frequency results in: Kp x Kv x Kn 1 = ------------------------------2 ( n) The maximum overshoot occurs at Nmax = 30; hence Kn = 130: 0.4 x 2.24 x 10 1 = ----------------------------------------- = 0.0012 2 5000 x 30 When C2 = 470 nF, it follows: 1 0.0012 R3' = ------- = --------------------------- = 2550 -9 C2 470 x 10 Hence the current source bias resistance Rb = 17 x 2550 = 43 k. With = 0.707 (0.5 x 2 x n) it follows: 0.707 2 = --------------------------- = 0.00028 0.5 x 5000 2 0.00028 R4 = ------- = --------------------------- = 600 -9 C2 470 x 10 For extra ripple suppression a capacitor C3 can be connected in parallel with R4, with an extra 3 = R4 x C3. For stability reasons 3 should be <0.12, hence C3 < 0.1C2, or C3 = 39 nF.
6
The VCO is set by the values of R1, R2 and C1; R2 = 10 k (adjustable). The values can be determined using the information in Table 3. With fc = 2.5 MHz and fL = 500 kHz this gives the following values (VCC = 5.0 V): R1 = 30 k. R2 = 30 k. C1 = 100 pF. The VCO gain is: 2f L x 2 K v = --------------------------------------------- = ( V CC - 1.1 ) - 1.1
6 1 MHz ---------------- x 2 2.24 x 10 r s V 2.8
=0
with the natural frequency n defined as: n = Kp x Kv x Kn ------------------------------- and the 1
damping value given as: = 0.5 x 2 x n In Fig.35 the output frequency response to a step of input frequency is shown. The overshoot and settling time percentages are now used to determine n. From Fig.35 it can be
1999 Jan 11
33
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Kp 100 kHz OSCILLATOR "HCU04" DIVIDE BY 10 "190" 14 3 PHASE COMPARATOR PC2 R3'
(1)
Kf 13 R4 C2 R1 9
Ko VCO 11 R2 C1
MBD098
4
f OUT
u
1 MHz
Kn PROGRAMMABLE DIVIDER "4059"
15 C3 Rb
12 6
7
5
R1 = 30 k. R2 = 30 k. C1 = 100 pF. R3' = 2550 . Rb = 43 k. R4 = 600 . C2 = 470 nF. C3 = 39 nF. (1) R3' = fictive resistance Rb R3' = -----17
Fig.34 Frequency synthesizer.
1.6
MGA959
-0.6 -0.4 -0.2
e (t) e / n
1.4
= 0.3
0.5 0.707 1.0
e (t) e / n
1.2
= 5.0
1.0
= 2.0
0
0.8
0.2
0.6 0.4
0.4 0.6
0.2
0.8
0
0
1
2
3
4
5
6
7
nt
8
1.0
Fig.35 Type 2, second order frequency step response.
1999 Jan 11
34
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Since the output frequency is proportional to the VCO control voltage, the PLL frequency response can be observed with an oscilloscope by monitoring pin 9 of the VCO. The average frequency response, as calculated by the Laplace method, is found experimentally by smoothing this voltage at pin 9 with a simple RC filter, whose time constant is long compared with the phase detector sampling rate but short compared with the PLL response time. Further information
3.1 proportional to output frequency (MHz) 3.0
MGA952
N = 30
N stepped from 29 to 30 2.9 step input 2.1 N stepped from 21 to 20 2.0
For an extensive description and application example please refer to "Application note" ordering number 9398 649 90011. Also available a "Computer design program for PLLs" ordering number 9398 961 10061.
1.9
0
0.5
1.0
1.5
2.0 2.5 time (ms)
Fig.36 Frequency compared to the time response.
1999 Jan 11
35
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
PACKAGE OUTLINES DIP16: plastic dual in-line package; 16 leads (300 mil); long body
74HCT9046A
SOT38-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 16 9 MH wM (e 1)
pin 1 index E
1
8
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.7 0.19 A1 min. 0.51 0.020 A2 max. 3.7 0.15 b 1.40 1.14 0.055 0.045 b1 0.53 0.38 0.021 0.015 c 0.32 0.23 0.013 0.009 D (1) 21.8 21.4 0.86 0.84 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.10 e1 7.62 0.30 L 3.9 3.4 0.15 0.13 ME 8.25 7.80 0.32 0.31 MH 9.5 8.3 0.37 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT38-1 REFERENCES IEC 050G09 JEDEC MO-001AE EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-10-02 95-01-19
1999 Jan 11
36
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 A1 pin 1 index Lp 1 e bp 8 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.010 0.057 0.004 0.049
0.019 0.0100 0.39 0.014 0.0075 0.38
0.244 0.041 0.228
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07S JEDEC MS-012AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-23 97-05-22
1999 Jan 11
37
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
SOLDERING Introduction This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Through-hole mount packages SOLDERING BY DIPPING OR BY SOLDER WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joints for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. MANUAL SOLDERING Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. Surface mount packages REFLOW SOLDERING Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. 1999 Jan 11 38 MANUAL SOLDERING
74HCT9046A
Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. WAVE SOLDERING Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
Suitability of IC packages for wave, reflow and dipping soldering methods
74HCT9046A
SOLDERING METHOD MOUNTING PACKAGE WAVE Through-hole mount DBS, DIP, HDIP, SDIP, SIL Surface mount BGA, SQFP HLQFP, HSQFP, HSOP, HTSSOP, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. 3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. suitable(2) not suitable not not not suitable(3) recommended(4)(5) recommended(6) suitable REFLOW(1) - suitable suitable suitable suitable suitable - - - - - DIPPING suitable
1999 Jan 11
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
SCA61
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
245002/00/03/pp40
Date of release: 1999 Jan 11
Document order number:
9397 750 05007

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